Telecommunication integrated circuits are typically required to exchange information with one or more data sources and data targets. A telecommunication integrated circuit may have a processor that can process data and then send it to the one or more data targets.
In many cases the data is sent to a FIFO memory unit (also referred to as FIFO) that can partially compensate for timing differences between FIFO read operations performed by a slow retrieving data target and FIFO write operations performed by a fast component. U.S. Pat. Nos. 5,712,992 of and 5,365,485, both being incorporated herein by reference, provide examples of prior art FIFO management methods and devices.
The FIFO has to be managed in order to prevent overwriting of valid information. The complexity of a FIFO management circuit increases when there are timing differences between the FIFO read and write operations and especially when the data target can request to retransmit data from the FIFO.
There is a need to provide efficient devices and methods for managing retransmit operations.